RISC-V : What Really Matters

Readers may have seen the recent blog post from Dmitri Grinberg RISC-V: They Should Have Known Better which sets out, at some length, his criticisms of the RISC-V architecture. Here’s a sample:Now, about those compressed instructions. Let us look at them in detail. They are hilariously poorly designed. Say you want to store a byte to a register plus offset. What range of offsets can a 16-bit instruction encode? Zero through three. Not thirty three, not three hundred and three. Three! Well, maybe...